Item type |
紀要論文 / Departmental Bulletin Paper(1) |
公開日 |
2023-03-30 |
タイトル |
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タイトル |
3次元VLSI設計のための5層チャネルルータの開発 |
タイトル |
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タイトル |
Development of a 5-layer Channel Router for 3-D VLSI Design |
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言語 |
en |
言語 |
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言語 |
jpn |
キーワード |
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主題Scheme |
Other |
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主題 |
VLSI |
キーワード |
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主題Scheme |
Other |
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主題 |
3-D |
キーワード |
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主題Scheme |
Other |
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主題 |
layout |
キーワード |
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主題Scheme |
Other |
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主題 |
channel |
キーワード |
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主題Scheme |
Other |
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主題 |
router |
資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
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資源タイプ |
departmental bulletin paper |
著者 |
大村, 道郎
岡本, 好広
Ohmura, Michiroh
Okamoto, Yoshihiro
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抄録 |
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内容記述タイプ |
Abstract |
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内容記述 |
Channel routing is one of the important problems in VLSI layout design. Many channel routing problems have been researched, and one of them is for multilayer channels in which terminals of different nets exist on a column. This problem cannot be solved by the conventional algorithms, which are designed for multilayer channels in which terminals of the same net exist on a column. It is referred to as the 3-D channel routing problem and any method for this problem is discussed on the design speed. In the research of devices in which circuit elements are integrated in 3-D, small chips have been developed since late 1980's. In the layout design that is necessary to develop large-scale 3-D integrated circuits, development of a high-speed routing method is indispensable. In this paper, a fast 5-layer routing method for 3-D rectangular channels is proposed based on the greedy router and it is extended for 3-D irregular channels. The experimental results to evaluate the proposed method are also shown. |
書誌情報 |
広島工業大学紀要. 研究編
巻 37,
p. 23-31,
発行日 2003
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出版者 |
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出版者 |
広島工業大学 |
ISSN |
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収録物識別子タイプ |
ISSN |
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収録物識別子 |
13469975 |
書誌レコードID |
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収録物識別子タイプ |
NCID |
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収録物識別子 |
AA11599110 |
フォーマット |
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内容記述タイプ |
Other |
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内容記述 |
application/pdf |
著者版フラグ |
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出版タイプ |
VoR |
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出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
日本十進分類法 |
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主題Scheme |
NDC |
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主題 |
549.7 |