{"created":"2023-07-25T10:27:52.810370+00:00","id":607,"links":{},"metadata":{"_buckets":{"deposit":"34650401-dbf6-4340-9eb6-1c86d82a4754"},"_deposit":{"created_by":2,"id":"607","owners":[2],"pid":{"revision_id":0,"type":"depid","value":"607"},"status":"published"},"_oai":{"id":"oai:it-hiroshima.repo.nii.ac.jp:00000607","sets":["1:17:214"]},"author_link":["2621","2619","2620","2618"],"item_10002_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2000","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"13","bibliographicPageStart":"7","bibliographicVolumeNumber":"34","bibliographic_titles":[{"bibliographic_title":"広島工業大学研究紀要"}]}]},"item_10002_description_19":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_10002_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"The departments of Electronic and Electrical Engineering of Hiroshima Institute of Technology have been teaching integrated circuit designs and processes of semiconductors since 1989. In Electronic Experiments III, students learn the primitive logic circuits such as NOT, AND, etc. and their combination circuits that are expressed by schematic logic design using Graphic Editor, one of MAX-Plus II applications. Designed circuits are programmed for the FPGA device and their operation of the designed circuits is confirmed by using push switches and LED. Almost all the students find it best to study the logic circuits using computers compared with the handwriting of logic circuits. In Electrical Experiments II, the logic circuits are designed to display each student number in seven segments LED and written in VHDL language, based on the counter circuits and the decoder circuits. Next, the logic synthesis and the simulation are conducted. Designed circuits as well as Electronic Experiments III are confirmed .","subitem_description_type":"Abstract"}]},"item_10002_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"広島工業大学"}]},"item_10002_source_id_11":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AN0021271X","subitem_source_identifier_type":"NCID"}]},"item_10002_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"03851672","subitem_source_identifier_type":"ISSN"}]},"item_10002_subject_21":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549.7","subitem_subject_scheme":"NDC"}]},"item_10002_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"田中, 武"},{"creatorName":"タナカ, タケシ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"2618","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"大村, 道郎"},{"creatorName":"オオムラ, ミチロウ","creatorNameLang":"ja-Kana"}],"nameIdentifiers":[{"nameIdentifier":"2619","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Tanaka, Takeshi","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"2620","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Ohmura, Michiroh","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"2621","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2023-03-30"}],"displaytype":"detail","filename":"kenkyukiyo34007.pdf","filesize":[{"value":"2.2 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"kenkyukiyo34007.pdf","url":"https://it-hiroshima.repo.nii.ac.jp/record/607/files/kenkyukiyo34007.pdf"},"version_id":"8382bbdc-de79-4b77-8c68-d675d1b0a79a"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"VLSI design","subitem_subject_scheme":"Other"},{"subitem_subject":"semiconductor process engineering","subitem_subject_scheme":"Other"},{"subitem_subject":"CAD","subitem_subject_scheme":"Other"},{"subitem_subject":"PLD","subitem_subject_scheme":"Other"},{"subitem_subject":"FPGA","subitem_subject_scheme":"Other"},{"subitem_subject":"VHDL","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"departmental bulletin paper","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"広島工業大学におけるVLSI設計・プロセス工学教育","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"広島工業大学におけるVLSI設計・プロセス工学教育"},{"subitem_title":"On an education of VLSI design and process engineering In Hiroshima Institute ofTechnology","subitem_title_language":"en"}]},"item_type_id":"10002","owner":"2","path":["214"],"pubdate":{"attribute_name":"公開日","attribute_value":"2023-03-30"},"publish_date":"2023-03-30","publish_status":"0","recid":"607","relation_version_is_last":true,"title":["広島工業大学におけるVLSI設計・プロセス工学教育"],"weko_creator_id":"2","weko_shared_id":-1},"updated":"2023-07-25T10:44:49.730682+00:00"}